3DDE300401 CMA121 直流电源模块

The baseband signal is then applied to the MAX2361 I/Q input, upconverted and amplified to 130.38MHz intermediate frequency through an orthogonal modulator and an intermediate frequency variable gain amplifier (VGA). IF routes out of the chip through a lumped component LC filter and then returns to the chip, where it is further upconverted to RF by a mirror suppression mixer and RF VGA. The output driver matching is achieved through an pull-up inductor and a series capacitor.

The IF LO signal is generated and regulated by an on chip frequency synthesizer, and the external energy storage and loop filter elements of 3DDE300401 CMA121 form an intermediate frequency phase-locked loop (PLL). There is also a 19.2MHz temperature compensated crystal oscillator on the outside, which can provide PLL reference frequency.

Although external RF VCO modules, loop filters, and internal RF PLL frequency synthesizers can be used, there is no necessary VCO module during testing. Therefore, RF LO is provided by an external signal generator to provide an appropriate high-end injection signal of approximately -9dBm.

The working mode, IF PLL divider, and IF VGA gain are set through a three wire bus interface software (see Figure 3), and 3DDE300401 CMA121 simultaneously uses an external voltage calibrator to simulate the digital to analog converter (DAC) voltage at the VGC pin. By using directional couplers to simultaneously measure power and linearity.